DocumentCode
1853079
Title
Floorplanning with alignment and performance constraints
Author
Tang, Xiaoping ; Wong, D.F.
Author_Institution
Texas Univ., Austin, TX, USA
fYear
2002
fDate
2002
Firstpage
848
Lastpage
853
Abstract
In this paper, we present a floorplanning algorithm based on sequence pair representation. Our floorplanner has the following important features: (1) It is explicitly designed for fixed-frame floorplanning, which is different from traditional well-researched min-area floorplanning. Moreover, we also show that it can be adapted to minimize total area. (2) It addresses the problem of handling alignment constraint which arises in bus structure. (3) It deals with performance constraint such as bounded net delay, while many existing floorplanners just minimize total wire length. (4) More importantly, even with all these constraints the algorithm is very fast in that it evaluates the feasibility of a sequence pair and translates to a floorplan in O(n log log n) time typically where n is the number of blocks and the number of constrained blocks is O(n), which is significantly faster than the O(n3) method operating on constraint graph. Our algorithm is based on computing the longest common subsequence of a pair of weighted sequences. Experimental results on MCNC benchmark for block placement show the promise of the method.
Keywords
circuit layout CAD; sequences; alignment constraint; bounded net delay; bus structure; fixed-frame floorplanning; floorplanning algorithm; performance constraint; sequence pair; total area minimization; total wire length; Algorithm design and analysis; Application specific integrated circuits; Computer applications; Delay effects; Design automation; Design engineering; Permission; Silicon; Very large scale integration; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2002. Proceedings. 39th
ISSN
0738-100X
Print_ISBN
1-58113-461-4
Type
conf
DOI
10.1109/DAC.2002.1012740
Filename
1012740
Link To Document