Title :
A 1.6–880MHz synthesizable ADPLL in 0.13um CMOS
Author :
Chang, Hsiang Hui ; Lee, Shang Ming ; Chou, Chao Wen ; Chang, Yu Tung ; Cheng, Yi Li
Author_Institution :
MediaTek Inc., Hsinchu
Abstract :
A synthesizable all digital phase-locked loop (ADPLL) with an improved DCO and a frequency-bouncing-reduced algorithm is presented. The ADPLL covers 1.6-880 MHz frequency range while maintaining high frequency resolution. The synthesizable ADPLL can be easily migrated to different processes and foundries; requires less design time and maintain effort; and directly benefit from CMOS technology scaling. The PLL is fabricated in a 0.13-mum 1P6M high-Vt CMOS process and occupies an active area of 220 x 220 um2. The PLL consumes a maximum power of 16 mW and has 114 ps peak-to-peak jitter at 880 MHz.
Keywords :
CMOS digital integrated circuits; digital phase locked loops; jitter; oscillators; 1P6M high-Vt CMOS process; CMOS technology scaling; digital-controlled oscillator; frequency 1.6 MHz to 880 MHz; frequency-bouncing-reduced algorithm; peak-to-peak jitter; power 16 mW; size 0.13 mum; synthesizable ADPLL; synthesizable all digital phase-locked loop; time 114 ps; CMOS process; CMOS technology; Calibration; Circuit synthesis; Clocks; Delay; Digital filters; Frequency; Jitter; Phase locked loops;
Conference_Titel :
VLSI Design, Automation and Test, 2008. VLSI-DAT 2008. IEEE International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4244-1616-5
Electronic_ISBN :
978-1-4244-1617-2
DOI :
10.1109/VDAT.2008.4542400