DocumentCode :
1853236
Title :
A framework for evaluating design tradeoffs in packet processing architectures
Author :
Thiele, Lothar ; Chakraborty, Samarjit ; Gries, Matthias ; Künzli, Simon
Author_Institution :
Comput. Eng. & Networks Lab., Swiss Fed. Inst. of Technol., Switzerland
fYear :
2002
fDate :
2002
Firstpage :
880
Lastpage :
885
Abstract :
We present an analytical method to evaluate embedded network packet processor architectures, and to explore their design space. Our approach is in contrast to those based on simulation, which tend to be infeasible when the design space is very large. We illustrate the feasibility of our method using a detailed case study.
Keywords :
computer architecture; embedded systems; analytical model; design space exploration; embedded network; packet processor architecture; Computer architecture; Computer networks; Delay; Hardware; Permission; Resource management; Space exploration; Space technology; Throughput; Traffic control;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2002. Proceedings. 39th
ISSN :
0738-100X
Print_ISBN :
1-58113-461-4
Type :
conf
DOI :
10.1109/DAC.2002.1012746
Filename :
1012746
Link To Document :
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