Title :
Instruction decode mechanism for embedded real-time Java processor JPOR-32
Author :
Hu, Guang ; Chai, Zhilei ; Zhao, Wenke ; Tu, Shiliang
Author_Institution :
Dept. of Comput. Sci., Shanghai Int. Studies Univ., Shanghai, China
Abstract :
In this paper, taking JPOR-32 as an example, the mechanism of instruction decode (ID) for embedded real-time Java processor is presented. In light of the complex format of Java bytecodes instructions and the predictable requirement, a two-stage ID mechanism which provides effective support for predictability and efficiency of the processor is adopted. In ID stage one, complex instructions are converted to microinstructions through the mechanism of microprogram address mapping, and the reorganization of bytecodes instructions is performed with buffer. ID stage two provides architectural support for operands revision for predictable WCET, assists stage one in instruction recognition and conversion, and generates control signals for the following execution and memory access stage.
Keywords :
Java; decoding; program processors; JPOR-32; Java bytecodes instructions; embedded real-time Java processor; instruction decode mechanism; Buffer storage; Engines; Java; Process control; Real time systems; Registers; Java processor; embedded system; instruction decode; real-time Java;
Conference_Titel :
Electronics and Information Engineering (ICEIE), 2010 International Conference On
Conference_Location :
Kyoto
Print_ISBN :
978-1-4244-7679-4
Electronic_ISBN :
978-1-4244-7681-7
DOI :
10.1109/ICEIE.2010.5559792