DocumentCode :
1853698
Title :
A deep sub-micron timing measurement circuit using a single-stage Vernier delay line
Author :
Chan, Antonio H. ; Roberts, Gordon W.
Author_Institution :
Microelectron. & Comput. Syst. Lab., McGill Univ., Montreal, Que., Canada
fYear :
2002
fDate :
2002
Firstpage :
77
Lastpage :
80
Abstract :
On-chip timing and jitter measurement is one of the major challenges in recent years for characterizing high-speed analog and mixed-signal circuits. Although the Vernier delay line (VDL) method is a common approach to provide high timing resolution, its performance is limited by differential nonlinearity timing errors created by component mismatches. In this paper, a single-stage VDL approach is proposed in an attempt to reduce element-matching requirements. A custom IC was designed and fabricated in a 0.18 μm CMOS process. The design requires a silicon area of 0.12 mm2 and measured results indicate a timing resolution of 67 ps.
Keywords :
CMOS integrated circuits; VLSI; delay lines; mixed analogue-digital integrated circuits; timing jitter; 0.18 micron; CMOS; VDL; component mismatches; custom IC; deep sub-micron timing measurement circuit; differential nonlinearity timing errors; element-matching requirements; jitter measurement; mixed-signal circuits; on-chip timing; single-stage Vernier delay line; timing resolution; Analog computers; Clocks; Counting circuits; Delay lines; Histograms; Laboratories; Microelectronics; Performance evaluation; Propagation delay; Timing jitter;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002
Print_ISBN :
0-7803-7250-6
Type :
conf
DOI :
10.1109/CICC.2002.1012770
Filename :
1012770
Link To Document :
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