A code generation algorithm of crosstalk-avoidance code with memory for low-power on-chip bus

Author

Cheng, Kuang Chin ; Jou, Jing Yang

fYear

2008

fDate

23-25 April 2008

Firstpage

172

Lastpage

175

Abstract

In this paper, a bus encoding approach including related code generation algorithm for global data busses is developed to produce area-efficient crosstalk-avoidance (CA) codes with considering low-power requirements. Proposed codes are codes with memory using overlapping boundary strategy. The probabilistic distribution of input data could be included to reduce the power consumption. The performance improvement of CA codes is nearly 2times for heavily coupled busses based on theoretical analysis. As compared to uncoded data words, proposed codes show 12% to 38% energy- reduction on bus for an equi-probable 32-bit bus design.

Keywords

crosstalk; statistical distributions; system buses; area-efficient crosstalk-avoidance codes; bus encoding; code generation; global data bus; low-power on-chip bus; overlapping boundary strategy; power consumption; probabilistic distribution; theoretical analysis; uncoded data words; CMOS technology; Capacitance; Codecs; Crosstalk; Data engineering; Energy consumption; Integrated circuit interconnections; Power generation; Propagation delay; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation and Test, 2008. VLSI-DAT 2008. IEEE International Symposium on

Conference_Location

Hsinchu

Print_ISBN

978-1-4244-1616-5

Electronic_ISBN

978-1-4244-1617-2

Type

conf

DOI

10.1109/VDAT.2008.4542440

Filename

4542440