DocumentCode :
1853958
Title :
Hardware implementation of genetic algorithms using FPGA
Author :
Tang, Wallace ; Yip, Leslie
Author_Institution :
Dept. of Electron. Eng., City Univ. of Hong Kong, Kowloon, China
Volume :
1
fYear :
2004
fDate :
25-28 July 2004
Abstract :
In this paper, a hardware implementation of genetic algorithm using field-programmable gate arrays (FPGAs) is described and implemented. Such development can greatly improve the speed of genetic algorithm by the hardware parallel and pipelined architectures. In our design, various configurations of parallelization are available with a PCI board based design, which further helps in forming a fast optimization tool for real-world applications.
Keywords :
circuit optimisation; field programmable gate arrays; genetic algorithms; logic design; parallel architectures; peripheral interfaces; pipeline processing; FPGA; PCI board based design; field programmable gate arrays; genetic algorithms; hardware implementation; hardware parallel architectures; pipelined architectures; Algorithm design and analysis; Application software; Application specific integrated circuits; Field programmable gate arrays; Genetic algorithms; Hardware; Prototypes; Random access memory; Read-write memory; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on
Print_ISBN :
0-7803-8346-X
Type :
conf
DOI :
10.1109/MWSCAS.2004.1354049
Filename :
1354049
Link To Document :
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