Title :
Single-chip FEC codec LSI using iterative CSOC decoder for 10 Gb/s long-haul optical transmission systems
Author :
Seki, K. ; Mikami, Kousuke ; Baba, M. ; Katayama, A. ; Tanaka, H. ; Hara, Y. ; Kobayashi, M. ; Okada, N.
Author_Institution :
NEC Corp., Kanagawa, Japan
Abstract :
This paper describes a 10 Gb/s throughput FEC (Forward Error Correction) codec LSI for long-haul optical transmission systems. The FEC codec uses concatenated Reed-Solomon (255,239) and Convolutional Self Orthogonal Code (CSOC). In order to improve the error correction capability, the FEC code applies iterative CSOC decoding. As a result, the FEC codec provides 8.0 dB net coding gain at 1E-12 corrected bit error rate with 25% redundancy. Due to the low complexity of CSOC, the codec achieves a low power consumption of 3.59 W and a low gate count of 1.32 Mgates using 0.18 μm CMOS technology.
Keywords :
CMOS digital integrated circuits; Reed-Solomon codes; VLSI; codecs; concatenated codes; convolutional codes; digital communication; digital signal processing chips; error statistics; forward error correction; iterative decoding; low-power electronics; optical communication equipment; optical fibre communication; redundancy; 0.18 micron; 10 Gbit/s; 3.59 W; 8 dB; BER; CMOS technology; RS code; bit error rate; concatenated Reed-Solomon code; convolutional self orthogonal code; forward error correction codec; iterative CSOC decoder; long-haul DWDM systems; long-haul optical transmission systems; low power consumption; single-chip FEC codec; CMOS technology; Codecs; Concatenated codes; Convolutional codes; Error correction codes; Forward error correction; Iterative decoding; Large scale integration; Reed-Solomon codes; Throughput;
Conference_Titel :
Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002
Print_ISBN :
0-7803-7250-6
DOI :
10.1109/CICC.2002.1012787
