Power efficient low latency survivor memory architecture for Viterbi decoder

Viterbi decoder is a common module in communication system in which power and decoding latency are constraint. Register exchange (RE) architecture has the lowest decoding latency L. However, it is not suitable for communication system because of its high power consumption. In this paper, we propose a new SMU architecture which combines the concept of the trace-forward and trace-back. The decoding latency of the proposed SMU algorithm is only L+M. Besides, we present a power efficient architecture for the proposed SMU algorithm. We implement the proposed architecture in TSMC 0.13 mum technology. The power consumption of the proposed architecture is slightly higher than the 3-pointer even TB architecture.