A two-stage charge-based analog/digital neuron circuit with adjustable weights

Author

Schmid, Alexandre ; Leblebici, Yusuf ; Mlynek, Daniel

Author_Institution

Integrated Syst. Center, Swiss Fed. Inst. of Technol., Lausanne, Switzerland

Volume

4

fYear

1999

fDate

1999

Firstpage

2357

Abstract

A circuit-level neuron architecture based on the principle of analog charge-based computation of neural functions has been developed with the goals of high-speed processing, adjustable weights, and support of perturbation-based learning algorithms. The two-stage architecture which is composed of nonlinear synapses, driving a linear capacitive soma, has been implemented using a conventional double-polysilicon CMOS technology. The feedforward architecture of the proposed neuron model is shown to synthesize a large number of nonlinear mappings of the 2D-1D space

Keywords

CMOS integrated circuits; feedforward neural nets; learning (artificial intelligence); mixed analogue-digital integrated circuits; neural chips; neural net architecture; adjustable weights; circuit-level neuron architecture; conventional double-polysilicon CMOS technology; feedforward architecture; linear capacitive soma; nonlinear mappings; nonlinear synapses; two-stage charge-based analog/digital neuron circuit; Analog computers; Artificial neural networks; CMOS technology; Capacitance; Computer architecture; Hardware; Integrated circuit technology; Inverters; Neurons; USA Councils;

fLanguage

English

Publisher

ieee

Conference_Titel

Neural Networks, 1999. IJCNN '99. International Joint Conference on

Conference_Location

Washington, DC

ISSN

1098-7576

Print_ISBN

0-7803-5529-6

Type

conf

DOI

10.1109/IJCNN.1999.833434

Filename

833434