High-speed VLSI architecture for low-complexity chase soft-decision Reed-Solomon decoding

Interpolation-based algebraic soft-decision decoding (ASD) of Reed-Solomon (RS) codes can achieve significant coding gain with polynomial complexity. Among available ASD algorithms, the low-complexity chase (LCC) algorithm can achieve a good performance-complexity tradeoff. In addition, the multiplicity of each interpolation point involved in this algorithm is one. These features make the LCC decoding very attractive for practical hardware implementation. In this paper, we present an efficient and high-speed VLSI architecture for the implementation of the LCC decoder. ASD algorithms have two major steps: interpolation and factorization. The high efficiency of the LCC interpolation architecture is achieved by employing a backward interpolation technique, which enables the sharing of intermediate interpolation results. We also show that the factorization step can be eliminated in the case of LCC decoding. From critical path and latency analysis, the LCC decoder can achieve a throughput of several gigabits per second in ASIC implementations. In addition, the LCC decoder requires less than three times the area of a hard-decision decoder that has the same throughput.