Title :
2400-MFLOPS reconfigurable parallel VLSI processor for robot control
Author :
Fujioka, Yoshichika ; Kameyama, Michitaka
Author_Institution :
Tohoku Univ., Sendai, Japan
Abstract :
The architecture of a floating-point reconfigurable parallel VLSI processor is proposed to reduce the latency for robot control, because the computation is performed in a feedback loop. In each processor element, switching hardware is used to change the connection between the multipliers and the adders, so that the multiply-adders having the desired number of multipliers can be reconstructed. Since the data transfer is performed by direct connection between the multipliers and adders, the overhead for data transfer is reduced. The chip evaluation based on 0.8-μm CMOS design rule shows that the latency for resolved acceleration control computation of a twelve-degrees-of-freedom redundant manipulator becomes about 32 μs, which is about sixty times faster than that of a parallel processor approach using conventional digital signal processors
Keywords :
CMOS integrated circuits; feedback; microcontrollers; parallel machines; reconfigurable architectures; robots; 0.8 micron; 12-d.o.f. redundant manipulator; 2400 MFLOPS; 32 mus; CMOS; control latency reduction; data transfer; feedback loop; floating-point reconfigurable parallel VLSI processor; resolved acceleration control; robot control; switching hardware; Adders; CMOS process; Computer architecture; Concurrent computing; Delay; Feedback loop; Hardware; Parallel robots; Robot control; Very large scale integration;
Conference_Titel :
Robotics and Automation, 1993. Proceedings., 1993 IEEE International Conference on
Conference_Location :
Atlanta, GA
Print_ISBN :
0-8186-3450-2
DOI :
10.1109/ROBOT.1993.291857