• DocumentCode
    1865599
  • Title

    Performance impacts of caching I-structure data on frame-based multithreaded processing

  • Author

    Kim, Hyong-Shik ; Ha, Soonhoi ; Jhon, Chu Shik

  • Author_Institution
    Dept. of Comput. Eng., Seoul Nat. Univ., South Korea
  • fYear
    1997
  • fDate
    28 Apr-2 May 1997
  • Firstpage
    24
  • Lastpage
    29
  • Abstract
    Since long latency due to remote memory access or interprocessor communication could be tolerated in multithreaded processing, caching I-structure memory is expected to have less beneficial effect on the performance than caching ordinary data. The authors suggest an organization and an operation scheme of an I-structure cache in frame-based multithreading, and show quantitatively that caching I-structure memory could improve the overall performance, in spite of the latency tolerating property of multithreading. With I-structure caches, the performance impacts are three-fold: a reduction of average latency; an increase of quantum size; and enhancement of frame parallelism. Among them, the enhancement of frame parallelism seems most important
  • Keywords
    cache storage; virtual machines; I-structure data caching; I-structure memory caching; frame parallelism; frame-based multithreaded processing; interprocessor communication; latency tolerance; performance impact; remote memory access; Communication switching; Context modeling; Costs; Data engineering; Delay; Multithreading; Parallel processing; Performance analysis; Switches; Yarn;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Performance Computing on the Information Superhighway, 1997. HPC Asia '97
  • Conference_Location
    Seoul
  • Print_ISBN
    0-8186-7901-8
  • Type

    conf

  • DOI
    10.1109/HPC.1997.592116
  • Filename
    592116