Memory latency and thread migration challenges for distributed shared memory systems

Distributed shared memory systems have received considerable interest since the concept was originally proposed by Kai Li (1986). In such systems networks of workstations can be used to solve computationally intensive problems. Straightforward implementation of DSMs have suffered performance penalties. This has led to various relaxed memory consistency models that offer opportunities for optimizing performance of DSM systems. To further improve the performance and eliminate false sharing, various DSM systems have tried numerous ad hoc techniques (e.g. combining several messages into a single message, permitting multiple writers to the same page). In a majority of these systems, the DSMs have been implemented on top of an existing OS kernel. This in itself has limited the performance as well as flexibility. The authors propose a new multithreaded-architecture for tolerating memory latencies. They also present some challenges to DSM system for supporting the multithreaded programming model and how the new architectures can aid in this regard