DocumentCode
1868709
Title
A 1.8 V, 1 MS/s, 85 dB SNR 2+2 mash /spl Sigma//spl Delta/ modulator with /spl plusmn/0.9 V reference voltage
Author
Kye-Shin Lee ; Maloberti, F.
Author_Institution
Dept. of Electr. Eng., Texas Univ., Richardson, TX, USA
fYear
2003
fDate
12-14 June 2003
Firstpage
71
Lastpage
74
Abstract
A 1.8 V, 1 MS/s, 85 dB SNR 2+2 mash /spl Sigma//spl Delta/ modulator with /spl plusmn/0.9 V reference voltage is realized by using the swing reduction structure. This structure limits the output swing of all the integrators within half the reference voltage. Thus, low voltage and high speed operation is possible with even high reference voltage without degrading the performance of the modulator. The circuit is fabricated in CMOS 0.35 /spl mu/m process with chip size of 2.5/spl times/2.5 mm/sup 2/.
Keywords
CMOS integrated circuits; delta-sigma modulation; modulators; /spl Sigma//spl Delta/ modulator; 0.35 micron; 1.8 V; 2.5 mm; 85 dB; CMOS process; SNR; integrators; reference voltage; signal-noise ratio; swing reduction structure; Circuits; Degradation; Delta modulation; Digital modulation; Feedback loop; Multi-stage noise shaping; Output feedback; Signal processing; Transfer functions; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on
Conference_Location
Kyoto, Japan
Print_ISBN
4-89114-034-8
Type
conf
DOI
10.1109/VLSIC.2003.1221165
Filename
1221165
Link To Document