Title :
Reliability evaluation of multivalued logic circuits via probabilistic transfer matrices
Author :
Abbasinasab, A. ; Yanushkevich, S.N.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Calgary, Calgary, AB, Canada
fDate :
April 29 2012-May 2 2012
Abstract :
This paper is concerned with reliability evaluation for logic networks. The proposed approach is based on the notation of probabilistic transfer matrices (PTM), which is extended from binary to multivalued gates and circuits. The presented approach models all sources of uncertainty in the multivalued circuits, including faulty gates, noisy signals and unreliable interconnections, in order to derive the overall reliability of a given multivalued circuit.
Keywords :
integrated circuit interconnections; integrated circuit reliability; logic gates; matrix algebra; multivalued logic circuits; PTM; faulty gates; logic networks; multivalued gates; multivalued logic circuits; noisy signals; probabilistic transfer matrices; reliability evaluation; unreliable interconnections; Error probability; Integrated circuit modeling; Integrated circuit reliability; Logic gates; Multivalued logic; Probabilistic logic; multivalued logic circuits; probabilistic model; probability transfer matrix; reliability evaluation;
Conference_Titel :
Electrical & Computer Engineering (CCECE), 2012 25th IEEE Canadian Conference on
Conference_Location :
Montreal, QC
Print_ISBN :
978-1-4673-1431-2
Electronic_ISBN :
0840-7789
DOI :
10.1109/CCECE.2012.6334965
