A sample preparation methodology to reduce sample edge unevenness and improve efficiency in delayering the 20-nm node IC chips

Author

Feng, H. ; Tan, P.K. ; Yap, H.H. ; Low, G.R. ; He, R. ; Zhao, Y.Z. ; Liu, B. ; Dawood, M.K. ; Zhu, J. ; Huang, Y.M. ; Wang, D.D. ; Tan, H. ; Lam, J. ; Mai, Z.H.

Author_Institution

GLOBALFOUNDRIES Singapore Pte Ltd., Singapore, Singapore

fYear

2015

fDate

June 29 2015-July 2 2015

Firstpage

459

Lastpage

464

Abstract

With continuous scaling of Complementary Metal Oxide Semicondutor (CMOS) device dimensions, traditional inter-level dielectrics have be replaced by low-k materials, because of the advantages of ultra low-k material such as lower parasitic capacitance, lower cross talk effects, and lower RC delay. The new material in integrated circuits (IC) makes physical failure analysis (PFA) more challenging. This paper presents a sample preparation methodology for reducing the sample deprocess edging effect with an efficient way on delayering the 20-nm node IC chips. We combined several delayering techniques to achieve an excellent flatness surface and improve the time efficiency for PFA on 20nm technology.

Keywords

CMOS integrated circuits; failure analysis; integrated circuit interconnections; low-k dielectric thin films; CMOS device; IC chip; PFA; complementary metal oxide semicondutor device; integrated circuits; interlevel dielectrics; lower RC delay; lower cross talk effects; parasitic capacitance; physical failure analysis; sample edge unevenness; sample preparation methodology; size 20 nm; ultra low-k material; Chemicals; Etching; Failure analysis; Inspection; Integrated circuits; Metals;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits (IPFA), 2015 IEEE 22nd International Symposium on the

Conference_Location

Hsinchu

Type

conf

DOI

10.1109/IPFA.2015.7224432

Filename

7224432