• DocumentCode
    1869965
  • Title

    A wide range 1.0 V-3.6 V 200 Mbps, push-pull output buffer using parasitic bipolar transistors

  • Author

    Shimada, T. ; Notani, H. ; Nakase, Y. ; Makino, H. ; Iwade, S.

  • Author_Institution
    Syst. LSI Dev. Center, Mitsubishi Electr. Corp., Hyogo, Japan
  • fYear
    2003
  • fDate
    12-14 June 2003
  • Firstpage
    243
  • Lastpage
    246
  • Abstract
    We proposed a push-pull output buffer that maintains the data transmission rate for lower supply voltages. It operates at an internal supply voltage (VDD) of 0.7-1.6 V and an interface supply voltage (VDDX) of 1.0-3.6 V. In low VDDX operation, the output buffer utilizes parasitic bipolar transistors instead of MOS transistors to maintain drivability. Furthermore forward body bias control is provided for the level converter in low VDD operation. We fabricated a test chip with a standard 0.15 /spl mu/m CMOS process. Measurement results indicate that the proposed output buffer achieves 200 Mbps operation at VDD of 0.7 V and VDDX of 1.0 V.
  • Keywords
    CMOS integrated circuits; bipolar transistors; buffer circuits; 1 to 3.6 V; 200 Mbit/s; CMOS; level converter; parasitic bipolar transistors; push-pull output buffer; test chip; Bipolar transistors; CMOS process; Data communication; Driver circuits; Energy consumption; Intrusion detection; Large scale integration; MOSFETs; Protection; Threshold voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on
  • Conference_Location
    Kyoto, Japan
  • Print_ISBN
    4-89114-034-8
  • Type

    conf

  • DOI
    10.1109/VLSIC.2003.1221216
  • Filename
    1221216