Title :
A pico-joule class, 1 GHz, 32 KByte/spl times/64 b DSP SRAM with self reverse bias
Author :
Bhavnagarwala, A.J. ; Kosonocky, S.V. ; Immediato, M. ; Knebel, D. ; Haen, A.-M.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
New SRAM circuit techniques implemented in a standard 0.13 /spl mu/m bulk Si CMOS process are reported in this work that (i) enable pico-joule energy dissipation per accessed bit at 1 GHz, (ii) lower total leakage power by over 80% from all unaccessed cells, during both active and standby modes, using a rigorous, self reverse biasing scheme that addresses leakage due to quantum tunneling and thermal excitation in all cell transistors, with an area, performance and noise margin penalty of less than 3% each and (iii) enable a programmable leakage reduction option that lowers leakage by over 90% when stored data is no longer desired.
Keywords :
CMOS integrated circuits; SRAM chips; digital signal processing chips; elemental semiconductors; field effect transistors; silicon; tunnelling; 0.13 micron; 1 GHz; DSP SRAM; Si; Si CMOS process; cell transistors; energy dissipation; pico joule class; quantum tunneling; self reverse bias; thermal excitation; unaccessed cells; Circuits; Clocks; Decoding; Delay; Digital signal processing; Pulse amplifiers; Pulse generation; Random access memory; Space vector pulse width modulation; Voltage;
Conference_Titel :
VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-034-8
DOI :
10.1109/VLSIC.2003.1221218
