Design for testability of on-line multipliers

This paper deals with the test of an integrated on-line multiplier suitable for very large numbers. Due to the serial structure of the circuit, the controllability and observability of the different elements are very low. In particular, an embedded sequential array cannot be accessed directly and has no primary outputs. Therefore, we propose here two DFT alternatives. The first one determines the most significant nodes to be considered in order to avoid error masking. The second approach increases the parallelism of the circuit and presents, thus, the advantage of a large reduction in the test duration. Both options have a low area overhead and a reduced number of extra pins