Author :
Grudowski, P. ; Dhandapani, V. ; Zollner, S. ; Goedeke, D. ; Loiko, K. ; Tekleab, D. ; Adams, V. ; Spencer, G. ; Desjardins, H. ; Prabhu, L. ; Garcia, R. ; Foisy, M. ; Theodore, D. ; Bauer, M. ; Weeks, D. ; Thomas, S. ; Thean, A. ; White, B.
Abstract :
We report a CMOS-compatible embedded silicon-carbon (eSiC) source/drain stressor technology with NMOS performance enhancement. The integration includes up to 2.6% substitutional carbon (Csub) epitaxial Si:C and laser spike annealing (LSA) for increased Csub incorporation. 26% channel resistance (Rch) reduction and 11% Idlin-Ioff enhancement for 0.5% Csub and 60% Rch reduction for 2.2% Csub are demonstrated.
Keywords :
CMOS integrated circuits; MOS integrated circuits; carbon; laser beam annealing; silicon; silicon compounds; silicon-on-insulator; CMOS integration; NMOS performance enhancement; SOI; Si-SiO2; Si:C; carbon incorporation; channel resistance; embedded silicon-carbon source-drain stressor technology; laser spike annealing; Annealing; CMOS process; CMOS technology; Degradation; Doping; Epitaxial growth; MOS devices; Rapid thermal processing; Silicon carbide; Tensile stress;