Measurement of Thermal Time Constant in 65-nm PD-SOI Technology with Sub-ns Resolution

In PD-SOI the oxide layer between MOSFETs and the underlying silicon substrate presents a thermal resistance that can lead to significant temperature rise for power dissipating devices. This can impact circuit performance and also introduce differences between device characteristics measured under DC conditions and those experienced under "at speed" operating conditions with low duty cycles common for CMOS circuits. Here a new technique for measuring the thermal time constant of PD-SOI MOSFETs in an adjacent heating configuration with sub-ns time resolution is presented. Experimental results for specific layouts in experimental 65 nm PD-SOI hardware show time constants of order 20 - 30 ns.