Title :
Aliasing error for a mask ROM built-in self-test
Author :
Iwasaki, Kazuhiko ; Furuta, Akinori ; Nakamura, Shigeo
Author_Institution :
Fac. of Eng., Chiba Univ., Japan
Abstract :
The aliasing probability is theoretically analyzed for a mask ROM containing a word/bit-line fault or faults within a mat. Analysis of 1000 faulty mask ROM chips revealed cell faults, word-line faults, bit-line faults, delay faults and other types. For these chips, the BIST aliasing errors were experimentally examined. Six MISRs were implemented on a custom board, and aliasing errors were actually observed. The best of the six is shown to be the 16-stage, 8-input MISR with no aliasing error
Keywords :
built-in self test; errors; integrated circuit testing; integrated memory circuits; probability; read-only storage; BIST; MISR; ROM chips; aliasing error; aliasing probability; bit-line faults; built-in self-test; cell faults; delay faults; mask ROM; word-line faults; Built-in self-test; Circuit faults; Circuit testing; Combinational circuits; Decoding; Delay; NP-complete problem; Read only memory; Test pattern generators; Text processing;
Conference_Titel :
VLSI Test Symposium, 1994. Proceedings., 12th IEEE
Conference_Location :
Cherry Hill, NJ
Print_ISBN :
0-8186-5440-6
DOI :
10.1109/VTEST.1994.292328
