Title :
A Novel Two-Transistor Floating-Body Memory Cell
Author :
Fossum, J.G. ; Lu, Z. ; Zhang, W. ; Trivedi, V.P. ; Mathew, L. ; Sadd, M.
Author_Institution :
Univ. of Florida, Gainesville
Abstract :
In this paper we propose a novel two-transistor (2T) FBC for DRAM applications that can yield much better signal margin and density, while offering other significant advantages over the 1T cell. The key features of the 2T FBC are demonstrated via process/physics-based device/circuit simulations, supported by numerical results.
Keywords :
DRAM chips; MOS integrated circuits; silicon-on-insulator; 2T FBC; DRAM applications; SOI MOSFET; circuit simulations; signal density; signal margin; two-transistor floating-body memory cell; Acquired immune deficiency syndrome; Conference proceedings; FinFETs; Joining processes; MOSFET circuits; Numerical simulation; Partial discharges; Predictive models; Random access memory; Threshold voltage;
Conference_Titel :
SOI Conference, 2007 IEEE International
Conference_Location :
Indian Wells, CA
Print_ISBN :
978-1-4244-0879-5
Electronic_ISBN :
1078-621X
DOI :
10.1109/SOI.2007.4357874
