Fault Tolerant SoC Architecture Design for JPEG2000 using Partial Reconfigurability

In this paper, we present the design of a new architecture tolerating faults for the Image compression standard JPEG2000. The proposed fault tolerant design is based on adding a new reconfigurable core to the rest of the cores of the SoC. When a fault happens, it is tolerated using this reconfigurable core. The paper explains the hardware architecture allowing this inter-core communication toward fault tolerance. The target is to achieve a good reliability by this fault tolerance strategy and in the same time achieve the required speed allowing to the JPEG2000 to deal with video rather than still Image compression. The high speed is implemented using an optimized data organization and memories arrangement for the computation consuming blocks of the JPEG2000. The operating speed of the proposed architecture is 125 MHz for ALTERA FPGA implementation. The proposed architecture has increased the speed by a factor of 1.5, when compared to similar memory requiring architectures and decreased the memory requirement by a factor of 1.2, when compared to similar speed requiring architectures. Additionally, the proposed architecture achieves 91.45% fault coverage and it requires only 21% hardware overhead. The architecture has an optimum latency of 78.8 seconds corresponding to an optimum test sequence of n=985. The VHDL implementation of the six blocks of JPEG2000, corresponding to the full chain, has been developed and successfully validated on various types of ALTERA FPGA.