On the channel induced by sneak-path errors in memristor arrays

Memristors, also known as resistive RAMs, are very promising non-volatile media that can be packed in unprecedented density. However, the crossbar layout by which this high density is achieved entails major challenges arising from cell-to-cell interference. In particular, cell readout is affected by sneak paths, which are electric paths passing through other crossbar cells and affecting the outcome of the read operation. The existence of sneak paths and their severity depends upon the current bit assignment stored in the array. In this paper we study sneak-path errors by modeling the array as a single-parameter information theoretic channel. We calculate this parameter in closed form as a function of the array dimensions and the bias between 0s and 1s in the written bits. We extend this result to the case where error occurs only when at least L sneak-paths exist, and also examine the correlation between sneak-path errors in different cells within the array. The channel capacity is calculated in a flavor similar to the capacity of the Z channel, only with transition probability that depends on the array-bit distribution.