Effect of line-overlay and via-misalignment on dielectric reliability for different patterning schemes

Different advanced patterning schemes have been compared with respect to the effect of line-overlay and via-misalignment on dielectric reliability, where the effects on the Weibull slope, on the TDDB lifetime and on V_max were studied. The patterning schemes compared in this study are litho-etch-litho-etch and self-aligned-double-patterning. For typical intrinsic reliability parameters, in comparison with the ideal case of 0nm line-overlay and via-misalignment, the self-aligned-double-patterning scheme with a 3σ via-misalignment of 6nm leads to a V_max reduction of 26%. The additional line-overlay errors that must be taken into account for the litho-etch-litho-etch patterning scheme leads to a reduction of V_max by 43%.