DocumentCode
187629
Title
Lower trigger voltage design for ESD protection device applied in PMIC application
Author
Yi-Ning He ; Lu-An Chen ; Tien-Hao Tang ; Kuan-Cheng Su
Author_Institution
ESD Eng. Dept., United Microelectron. Corp., Hsinchu, Taiwan
fYear
2014
fDate
1-5 June 2014
Abstract
Lower trigger voltage ESD protection has been designed in PMIC application process. The proposed design lowers trigger voltage around 11% without extra mask layer and the layout diagram is simple and clear. The proposed device can be turned on quickly to protect the large array in output buffer design safely. It sustains 3.8kV human-body-model (HBM) and 350V machine model (MM) ESD tests, respectively.
Keywords
buffer circuits; electrostatic discharge; power supply circuits; trigger circuits; ESD protection device; ESD tests; HBM; PMIC application process; human body model; large array; machine model; output buffer design; trigger voltage design; voltage 3.8 kV; voltage 350 V; Arrays; Breakdown voltage; Electrostatic discharges; Layout; Leakage currents; Robustness; Voltage measurement; electrostatic discharge (ESD); trigger voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Reliability Physics Symposium, 2014 IEEE International
Conference_Location
Waikoloa, HI
Type
conf
DOI
10.1109/IRPS.2014.6861134
Filename
6861134
Link To Document