Title :
A single device based voltage step stress (VSS) technique for fast reliability screening
Author :
Ji, Zhen ; Zhang, Jian F. ; Zhang, Wensheng ; Zhang, Xiaobing ; Kaczer, Ben ; De Gendt, Stefan ; Groeseneken, Guido ; Ren, Pinyi ; Wang, Ruiqi ; Huang, R.
Author_Institution :
Sch. of Eng., Liverpool John Moores Univ., Liverpool, UK
Abstract :
A new wafer-level reliability qualification methodology is proposed. Unlike conventional method which usually takes days to completion, the total test time of the new technique can be shortened within 2 hours. Besides, it only requires a single device. This new technique is easy to implement on commercial equipment and it has been successfully validated on different processes including the most advanced 28nm process with both SiON and high-k gate stacks. This new technique can be an effective tool for fast reliability screening during process development in future.
Keywords :
MOSFET; high-k dielectric thin films; semiconductor device reliability; silicon compounds; stress analysis; SiON; VSS technique; fast reliability screening; high-k gate stacks; pMOSFET; single device based voltage step stress technique; size 28 nm; wafer-level reliability qualification methodology; Degradation; High K dielectric materials; Logic gates; MOSFET circuits; Reliability; Stress; Stress measurement; Bias tempeture instabilty; Lifetime predcition; Variabilty; defect generation; hole trapping;
Conference_Titel :
Reliability Physics Symposium, 2014 IEEE International
Conference_Location :
Waikoloa, HI
DOI :
10.1109/IRPS.2014.6861145
