Title :
Low Cost Launch-on-Shift Delay Test with Slow Scan Enable
Author :
Xu, Gefu ; Singh, Adit D.
Author_Institution :
Electr. & Comput. Eng., Auburn University, AL
Abstract :
Most scan based designs implement the scan enable as a slow speed global control signal, and can therefore only implement launch-on-capture (LOC) delay tests. Launch-on-shift (LOS) tests are generally more effective, achieving higher fault coverage with significantly fewer test vectors, but require a fast scan enable. We present a low cost solution for implementing LOS tests by adding a small amount of logic in each flip-flop to align the slow scan enable signal to the clock edge. Our new design is much more efficient when compared to other recent proposals, and can support full LOS testing. It can be further modified for mixed LOC/LOS tests that achieve TDF coverage approaching 95% for the ISCAS89 benchmarks
Keywords :
boundary scan testing; flip-flops; logic testing; clock edge; fault coverage; flip-flop; launch-on-capture delay tests; launch-on-shift delay test; scan based designs; slow scan enable; slow speed global control signal; Circuit faults; Circuit testing; Clocks; Costs; Delay; Flip-flops; Lab-on-a-chip; Logic testing; Signal design; Timing;
Conference_Titel :
Test Symposium, 2006. ETS '06. Eleventh IEEE European
Conference_Location :
Southampton
Print_ISBN :
0-7695-2566-0
DOI :
10.1109/ETS.2006.29
