Title :
Parallel architectures with flexible topology
Author :
Ledeczi, Akos ; Abbott, Ben
Author_Institution :
Dept. of Electr. Eng., Vanderbilt Univ., Nashville, TN, USA
Abstract :
Parallel computer architectures with flexible topology are ideal for compute intensive signal processing and instrumentation applications because they provide supercomputing performance and high I/O bandwidth. These systems can be implemented at low cost using processors like the transputer, the TMS320C40, or the ADSP-21060. However, due to difficulties with hardware and software complexity management, the number of successful large-scale applications is limited. Modeling the system graphically from multiple aspects-hardware and software-and automatically processing the models helps manage the complexity of these systems. The presented approach supports automatic topology verification, network loader configuration, process assignment, and deadlock-free message routing
Keywords :
digital signal processing chips; parallel architectures; reconfigurable architectures; signal processing; transputers; ADSP-21060; TMS320C40; automatic topology verification; compute intensive signal processing; deadlock-free message routing; flexible topology; instrumentation applications; network loader configuration; parallel architectures; process assignment; software complexity management; supercomputing performance; transputer; Application software; Bandwidth; Computer architecture; Concurrent computing; Costs; High performance computing; Instruments; Parallel architectures; Signal processing; Topology;
Conference_Titel :
Scalable High-Performance Computing Conference, 1994., Proceedings of the
Conference_Location :
Knoxville, TN
Print_ISBN :
0-8186-5680-8
DOI :
10.1109/SHPCC.1994.296654
