A power-efficient 32b ARM ISA processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation

Author

Bull, David ; Das, S. ; Shivshankar, K. ; Dasika, Ganesh ; Flautner, Krisztian ; Blaauw, D.

Author_Institution

ARM, Cambridge, UK

fYear

2010

fDate

7-11 Feb. 2010

Firstpage

284

Lastpage

285

Abstract

An ARM ISA processor fabricated in a 65nm CMOS process uses a combination of timing-error detecting circuits and micro-architectural recovery mechanisms to eliminate safety guardbands. Measurements performed on a distribution of 63 samples, including split lots, show a 52% power reduction for the overall distribution, for 1GHz operation.

Keywords

CMOS digital integrated circuits; compensation; error correction; error detection; integrated circuit design; microprocessor chips; ARM ISA processor; CMOS process; micro architectural recovery mechanisms; process voltage temperature variation; size 65 nm; timing error detecting circuits; timing-error detection; transient-error tolerance; word length 32 bit; Adaptive control; Automatic frequency control; Circuits; Clocks; Delay; Error correction; Instruction sets; Pipelines; Throughput; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

978-1-4244-6033-5

Type

conf

DOI

10.1109/ISSCC.2010.5433919

Filename

5433919

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1886396