DocumentCode :
1886690
Title :
Design of logarithmic encoder and error corrections
Author :
Chivapreecha, Sorawat ; Dejhan, Kobchai
Author_Institution :
King Mongkut´´s Inst. of Technol. Ladkrabang, Thailand
fYear :
2005
fDate :
18-20 May 2005
Firstpage :
15
Abstract :
Summary form only given. This paper presents the design of a binary logarithm for a logarithm radix-2 encoder. The circuit implementation uses combinational logic only and is based on Mitchell´s approximation algorithm. The error generated by the Mitchell´s algorithm is analyzed and is used to develop a method to design error correction circuits in order to improve the accuracy of the result. The area and speed characteristics of the proposed circuit design can be shown using an EPF10K20RC240-4 Altera FPGA for implementation. Finally, the error correction circuit that is used to reduce the error in the resulting logarithm approximation can be evaluated and a comparison can be made in the resulting error percentage to show its performance.
Keywords :
binary codes; coding errors; combinational circuits; digital arithmetic; encoding; error correction; field programmable gate arrays; FPGA implementation; Mitchell approximation algorithm; binary logarithm; combinational logic; error correction circuits; logarithm radix-2 encoder; logarithmic encoder; Algorithm design and analysis; Approximation algorithms; Circuit synthesis; Combinational circuits; Design methodology; Error correction; Field programmable gate arrays;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Nonlinear Signal and Image Processing, 2005. NSIP 2005. Abstracts. IEEE-Eurasip
Conference_Location :
Sapporo
Print_ISBN :
0-7803-9064-4
Type :
conf
DOI :
10.1109/NSIP.2005.1502234
Filename :
1502234
Link To Document :
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