On a New Graph Theory Approach to Designing Zero-Aliasing Space Compressors for Built-In Self-Testing

The design of space-efficient support hardware for built-in self-testing (BIST) is of great significance in the synthesis of present day very large scale integration (VLSI) circuits and systems, particularly in the context of design paradigm shift from system-onboard to system-on-chip (SOC). An approach to designing zero-aliasing space compaction hardware in relation to embedded cores-based SOC is proposed in this paper for single stuck-line faults, extending the well-known concepts of conventional switching theory, and of incompatibility relation to generate maximal compatibility classes (MCCs) using new graph theory concepts, based on optimal generalized sequence mergeability, as developed by the authors in earlier works. The paper briefly presents the mathematical basis of selection criteria for merger of an optimal number of outputs of the module under test (MUT) for realizing maximum compaction ratio in the design, along with some partial simulation results on ISCAS 85 combinational benchmark circuits, with programs ATALANTA and FSIM