Fault Detection and Diagnosis for Multi-Level Cell Flash Memories

Single bit per cell (SBC) flash memories have been widely used and many efficient testing and diagnosis methodologies have been proposed. On the other hand, their multi level cell counterparts are relatively not well-known, even though they have many advantages such as low area, high density, low power and short access time. To the best of our knowledge, no research papers have been published for multi level cell (MLC) flash memory testing and diagnosis. This paper is an attempt to bridge this gap by providing a simple solution to test and diagnose an MLC flash memory array. The fault model proposed takes into account many physical defects which cause the state of a memory cell to change. The universal test algorithm and the flash diagnosis (FDX) march algorithm proposed in this paper are a first of its kind for MLC flash. Their full fault coverage for the fault model we propose in this work, low complexity and test time make them an attractive methodology for testing and diagnosing faults for multi level flash memories