A 40GS/s 6b ADC in 65nm CMOS

Author

Greshishchev, Y.M. ; Aguirre, Juan ; Besson, M. ; Gibbins, Robert ; Falt, C. ; Flemke, P. ; Ben-Hamida, Naim ; Pollex, D. ; Schvan, P. ; Shing-Chi Wang

Author_Institution

Nortel, Ottawa, ON, Canada

fYear

2010

fDate

7-11 Feb. 2010

Firstpage

390

Lastpage

391

Abstract

A 6b 65nm CMOS ADC exceeds the 29GS/S requirement of a 58Gb/s DP-QPSK optical receiver while operating up to 40GS/S. An inter-leaved architecture combines 16 SAR converters and an array of T/Hs with delay, gain, and offset calibration. A 1V 40mW 2.5GS/S subADC results in a total power of 1.5W, ENOB of 4.5b (3.9b) up to 10GHz (18GHz). An on-chip signal synthesizer simplifies production testing.

Keywords

CMOS integrated circuits; analogue-digital conversion; calibration; optical receivers; polarisation; quadrature phase shift keying; signal synthesis; synthetic aperture radar; CMOS ADC; DP-QPSK optical receiver; SAR converters; analog-digital conversion; bit rate 58 Gbit/s; dual polarization; inter-leaved architecture; offset calibration; on-chip signal synthesizer; power 1.5 W; power 40 mW; production testing; size 65 nm; voltage 1 V; CMOS technology; Calibration; Circuits; Clocks; Frequency estimation; Packaging; Sampling methods; Switches; Synthesizers; Timing jitter;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

978-1-4244-6033-5

Type

conf

DOI

10.1109/ISSCC.2010.5433972

Filename

5433972