DocumentCode
1887865
Title
A 2.1Mpixel 120frame/s CMOS image sensor with column-parallel ΔΣ ADC architecture
Author
Youngcheol Chae ; Jimin Cheon ; Seunghyun Lim ; Dongmyung Lee ; Minho Kwon ; Kwisung Yoo ; Wunki Jung ; Dong-Hun Lee ; Seogheon Ham ; Gunhee Han
Author_Institution
Yonsei Univ., Seoul, South Korea
fYear
2010
fDate
7-11 Feb. 2010
Firstpage
394
Lastpage
395
Abstract
A 2.1 Mpixel 120 frame/s CMOS image sensor with column-parallel ΔΣ ADCs is realized in a 0.13 μm CMOS process. Column-parallel ΔΣ ADC architectures improve the conversion speed while reducing the random noise level as well. Inverter-based SC circuits maximize the power efficiency. This sensor achieves a measured noise floor of 1.9e-, while dissipating 180 mW.
Keywords
CMOS image sensors; analogue-digital conversion; delta-sigma modulation; δ-σ modulation; CMOS image sensor; analog-digital conversion; column parallel ΔΣ ADC architecture; conversion speed; inverter based SC circuits; power 108 mW; random noise level; size 0.13 μm; CMOS image sensors; Circuits; Detectors; Image sensors; Layout; Lighting; Pixel; Pulse width modulation; Sensor arrays; Video compression;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
978-1-4244-6033-5
Type
conf
DOI
10.1109/ISSCC.2010.5433974
Filename
5433974
Link To Document