A programmable built-in self-test core for embedded memories

Author

Huang, Chih-Tsun ; Huang, Jing-Reng ; Wu, Cheng-Wen

Author_Institution

Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan

fYear

2000

fDate

9-9 June 2000

Firstpage

11

Lastpage

12

Abstract

Testing embedded memories is becoming an industry-wide concern with the advent of deep-submicron technology and system-on-chip applications. We present a prototype chip for a programmable built-in self-test (BIST) design that is used for testing embedded memories, especially DRAMs. The BIST chip supports various memory test algorithms by a novel controller and sequencer design. The area of the core circuit is about 1, 020/spl times/1, 020 /spl mu/m/sup 2/ using a 0.6 /spl mu/m CMOS process, and the clock speed is over 100 MHz.

Keywords

CMOS digital integrated circuits; VLSI; built-in self test; embedded systems; integrated circuit testing; logic testing; random-access storage; 0.6 micron; 100 MHz; CMOS; DRAMs; clock speed; controller design; deep-submicron technology; embedded memories; memory test algorithms; programmable built-in self-test core; sequencer design; system-on-chip applications; Algorithm design and analysis; Automatic testing; Built-in self-test; CMOS process; Circuit testing; Clocks; Electrical equipment industry; Prototypes; System testing; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific

Conference_Location

Yokohama, Japan

Print_ISBN

0-7803-5973-9

Type

conf

DOI

10.1109/ASPDAC.2000.835054

Filename

835054