DocumentCode
1889062
Title
A co-processor architecture for video scan-rate-conversion and spatial/temporal noise reduction
Author
Guo, Shaori ; Lin, Chien-Hsin ; Zhang, Zhengyu
fYear
2005
fDate
14-16 June 2005
Firstpage
34
Lastpage
38
Abstract
A co-processor architecture for video scan-rate-conversion and noise reduction is presented. Both motion compensated and non-motion compensated deinterlacing and up-conversion algorithms are supported. This enables the co-processor to process both standard definition TV and high definition TV signals at low cost, offering a viable solution for consumer applications.
Keywords
coprocessors; image denoising; motion compensation; television standards; video signal processing; coprocessor architecture; high definition TV signals; nonmotion compensated deinterlacing; spatial-temporal noise reduction; standard definition TV; up-conversion algorithms; video scan-rate-conversion; Coprocessors; Costs; Flat panel displays; Frequency; HDTV; Image converters; Motion compensation; Motion estimation; Noise reduction; TV;
fLanguage
English
Publisher
ieee
Conference_Titel
Consumer Electronics, 2005. (ISCE 2005). Proceedings of the Ninth International Symposium on
Print_ISBN
0-7803-8920-4
Type
conf
DOI
10.1109/ISCE.2005.1502337
Filename
1502337
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