Performance-optimal clustering with retiming for sequential circuits

We propose an exact clustering with retiming algorithm to minimize the clock period for sequential circuits. Without moving flip-flops (FFs) by retiming, conventional clustering algorithms can only handle combinational parts and therefore cannot achieve the best cycle time. Pan et al. [1998] have proposed an optimal algorithm under the unit gate delay model. We propose a more powerful and faster algorithm that produces optimal results even under the more realistic general gate delay model. Experimental results show that our algorithm is twice as fast as Pan´s.