A Radix-8 Log-MAP recursion VLSI architecture

Author

Jin, Faxun ; Tang, Jian ; Feng Wang, Zhong ; Guo, Li

Author_Institution

Dept. of Electron. Sci. & Technol., USTC, Hefei

fYear

2008

fDate

10-12 Nov. 2008

Firstpage

347

Lastpage

350

Abstract

This paper presents a high speed Radix-8 Log-MAP turbo decoder recursion architecture: algorithmic approximation and architectural optimization are incorporated in the proposed designs to reduce the critical path. The synthesis results show that the proposed design has a high throughput of 693 Mbps in 0.18 um CMOS technology, which is nearly 3 times higher than using conventional Radix-2 architecture. The hardware complexity is only linearly increased with the new design. The simulation with AWGN channel shows that the proposed design has generally less than 0.05 dB performance degradation from the true Log-MAP decoder.

Keywords

AWGN channels; CMOS integrated circuits; VLSI; decoding; turbo codes; AWGN channel; CMOS technology; VLSI architecture; algorithmic approximation; architectural optimization; bit rate 693 Mbit/s; high speed Radix-8 Log-MAP recursion; size 0.18 mum; turbo decoder recursion architecture; AWGN channels; Algorithm design and analysis; Approximation algorithms; CMOS technology; Decoding; Degradation; Design optimization; Hardware; Throughput; Very large scale integration; Log-MAP; Radix-8; Turbo code; VLSI;

fLanguage

English

Publisher

ieee

Conference_Titel

Communication Technology, 2008. ICCT 2008. 11th IEEE International Conference on

Conference_Location

Hangzhou

Print_ISBN

978-1-4244-2250-0

Electronic_ISBN

978-1-4244-2251-7

Type

conf

DOI

10.1109/ICCT.2008.4716263

Filename

4716263