Title :
Back gate effects in thick film SOI CMOS devices
Author :
Yallup, Kevin ; Lane, Bill ; Edwards, Shannon
Author_Institution :
Analog Devices, Limerick, Ireland
Abstract :
A 30-V bulk p-well CMOS process has been implemented on nominally 5-μm bonded SOI (silicon-on-insulator) wafers using trench isolation to produce fully dielectrically isolated devices. By a suitable choice of doping levels, the SOI version of the process can be made to have the same electrical parameters as the bulk version. However, back gate controlled leakage of the PMOS devices has been observed. Several solutions to this problem are possible, including modification of the silicon layer doping, modification of the silicon layer thickness, and controlling the potential of the handle wafer
Keywords :
CMOS integrated circuits; integrated circuit technology; leakage currents; semiconductor-insulator boundaries; 30 V; PMOS devices; Si layer doping; Si layer thickness; Si-SiO2; back gate controlled leakage; bonded SOI wafers; bulk p-well CMOS process; dielectrically isolated devices; doping levels; thick film SOI CMOS devices; trench isolation; Dielectric devices; Dielectric materials; Dielectric substrates; Low voltage; MOS devices; Medium voltage; Switches; Testing; Thick films; Wafer bonding;
Conference_Titel :
SOI Conference, 1991. Proceedings, 1991., IEEE International
Conference_Location :
Vail Valley, CO
Print_ISBN :
0-7803-0184-6
DOI :
10.1109/SOI.1991.162850
