Title :
Layout generation of array cell for NMOS 4-phase dynamic logic
Author :
Furuie, Makoto ; Song, Bao-Yu ; Yoshida, Yukihiro ; Onoye, Takao ; Shirawaka, I.
Author_Institution :
Dept. of Inf. Syst. Eng., Osaka Univ., Japan
Abstract :
An array cell (AC) architecture for the layout design is described, which is dedicated to low-power design by means of NMOS 4-phase dynamic logic. An AC is constructed of (M/spl times/N)+2 transistors so as to constitute each type of NMOS 4-phase logic gate. A graph theoretic approach is exploited in the layout design to reduce the layout area. A number of experimental results demonstrate the practicability of the proposed approach.
Keywords :
MOS logic circuits; circuit layout CAD; graph theory; high level synthesis; integer programming; integrated circuit layout; linear programming; logic arrays; 4-phase logic gate; NMOS 4-phase dynamic logic; array cell architecture; graph theoretic approach; layout design; layout generation; low-power design; CMOS logic circuits; Clocks; Delay; Design engineering; Logic arrays; Logic functions; Logic gates; MOS devices; MOSFETs; Variable structure systems;
Conference_Titel :
Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific
Conference_Location :
Yokohama, Japan
Print_ISBN :
0-7803-5973-9
DOI :
10.1109/ASPDAC.2000.835157
