Title :
A testability metric for path delay faults and its application
Author :
Tsai, Huan-Chih ; Cheng, Kwang-Ting ; Agrawal, Vishwani D.
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
Abstract :
In this paper, we propose a new testability metric for path delay faults. The metric is computed efficiently using a non-enumerative algorithm. It has been validated through extensive experiments and the results indicate a strong correlation between the proposed metric and the path delay fault testability of the circuit. We further apply this metric to derive a path delay fault test application scheme for scan-based BIST. The selection of the test scheme Is guided by the proposed metric. The experimental results illustrate that the derived test application scheme can achieve a higher path delay fault coverage in scan-based BIST. Because of the effectiveness and efficient computation of this metric, it can be used to derive other design-for-testability techniques for path delay faults.
Keywords :
built-in self test; circuit testing; design for testability; circuit testability metric; design-for-testability; nonenumerative algorithm; path delay fault; scan-based BIST; Automatic test pattern generation; Built-in self-test; Circuit faults; Circuit simulation; Circuit testing; Costs; Delay effects; Design for testability; Flip-flops; Timing;
Conference_Titel :
Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific
Conference_Location :
Yokohama, Japan
Print_ISBN :
0-7803-5973-9
DOI :
10.1109/ASPDAC.2000.835170