Implementation of a programmable neuron in 0.35μm CMOS process for multi-layer ANN applications

In this paper we have discussed about the design of a fully programmable neuron to be used in ANN´s. This neuron is composed of two parts. The first part is activation function circuit and the second part is analog multiplier used as synapse. The most important feature of proposed neuron is the programmability of activation function and high dynamic range of synapse. The other features of designed circuits are low power consumption and simple structure. Simulation results using HSpice software in 0.35μm CMOS technology have been presented to show high precision of the synapse and the compatibility between synapse and activation function. The Maximum power consumption of one synapse and activation function is 230μW.