A multiprocessor architecture for high speed network interconnections

Author

Zitterbart, M.

Author_Institution

Inst. for Telematics, Karlsruhe Univ.

fYear

1989

fDate

23-27 Apr 1989

Firstpage

212

Abstract

A multiprocessor architecture suitable for the implementation of high-speed gateways is presented. It is based on a horizontal and vertical subdivision of communication systems. The resulting architecture consists of several receive and send pipelines, where every receive and send pipeline is associated with one subnetwork connected to the gateway. The pipeline stages are implemented on several processors which are combined into a processor unit. The internal structure of each processor unit is adapted to the protocol functions that are to be implemented on it. The architecture comprises pipeline structures and array structures and thus permits temporal parallelism as well as spatial parallelism

Keywords

computer networks; multiprocessor interconnection networks; array structures; communication systems; computer networks; high speed network interconnections; high-speed gateways; multiprocessor architecture; pipeline structures; protocol functions; spatial parallelism; temporal parallelism; Computer interfaces; FDDI; High-speed networks; LAN interconnection; Local area networks; Parallel processing; Pipelines; Protocols; Telematics; Wide area networks;

fLanguage

English

Publisher

ieee

Conference_Titel

INFOCOM '89. Proceedings of the Eighth Annual Joint Conference of the IEEE Computer and Communications Societies. Technology: Emerging or Converging, IEEE

Conference_Location

Ottawa, Ont.

Print_ISBN

0-8186-1920-1

Type

conf

DOI

10.1109/INFCOM.1989.101456

Filename

101456