CMOS op-amp circuit synthesis with geometric programming models for layout-dependent effects

This paper addresses CMOS analog circuit synthesis in the nanometer process based on geometric programming models. In the current era of electronic integrated circuit (IC) manufacturing, the channel length modulation λ as well as the layout-dependent effects (LDE) such as the shallow trench isolation (STI) stress and the well proximity effect (WPE) must be considered in the circuit synthesis because of the more and more shrinking process. The STI is a popular isolation between active regions in advanced CMOS technologies but it causes stress and influences the mobility. The WPE is the characteristics variation for devices located near the edge of the well mask. In this paper, we provide the posynomial models of the analog circuit specification taking the λ into account as well as introducing the curve fitting to the STI stress and the WPE based on the BSIM model. In the design case of a typical CMOS op-amp, with these LDE-aware models, we optimized the circuit by the geometric programming (GP) and showed that the optimal results satisfied the specification by the simulation.