The design and implementation of a first-generation CELL processor - a multi-core SoC

Author

Pham, D. ; Asano, S. ; Bolliger, M. ; Day, M.N. ; Hofstee, H.P. ; Johns, C. ; Kahle, J. ; Kameyama, A. ; Keaty, J. ; Masubuchi, Y. ; Riley, M. ; Shippy, D. ; Stasiak, D. ; Suzuoki, M. ; Wang, M. ; Warnock, J. ; Weitzel, S. ; Wendel, D. ; Yamazaki, T. ; Ya

Author_Institution

IBM Syst. & Technol. Group, Austin, TX, USA

fYear

2005

fDate

9-11 May 2005

Firstpage

49

Lastpage

52

Abstract

The implementation of a first-generation CELL processor that supports multiple operating systems including Linux consists of a 64 bit power processor element (PPE) and its L2 cache, multiple synergistic processor elements (SPE) (B. Flachs et al.) each with its own local memory (LS) (T. Asano et al.), a high bandwidth internal element interconnect bus (EIB), two configurable non-coherent I/O interfaces, a memory interface controller (MIC), and a pervasive unit that supports extensive test, monitoring, and debug functions. In conclusion, special circuit techniques, rules for modularity and reuse, customized clocking structures, and unique power and thermal management concepts were applied to optimize the design.

Keywords

cache storage; integrated circuit design; microprocessor chips; system-on-chip; 64 bit; CELL processor; I/O interfaces; L2 cache; Linux; clocking structures; element interconnect bus; local memory; memory interface controller; multicore SoC; multiple operating systems; pervasive unit; power management; power processor element; synergistic processor elements; thermal management; Bandwidth; Circuit testing; Clocks; Integrated circuit interconnections; Linux; Microwave integrated circuits; Monitoring; Operating systems; Power system interconnection; Thermal management;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuit Design and Technology, 2005. ICICDT 2005. 2005 International Conference on

Print_ISBN

0-7803-9081-4

Type

conf

DOI

10.1109/ICICDT.2005.1502588

Filename

1502588