Early Functional Evaluation of SET Effects

Author

Hadjiat, K. ; Ammari, A. ; Leveugle, R.

Author_Institution

TIMA Lab., Grenoble

fYear

2005

fDate

19-23 Sept. 2005

Abstract

Fault injection in VHDL descriptions has become an efficient solution to analyze at an early stage of the design the potential faulty behaviors of a complex digital circuit. Classical injection campaigns are based on the "single bit-flip" fault model, representative of single event upsets (SEUs). Single event transients (SETs) are becoming more important with very deep sub-micron technologies and require different early analyses strategies. This paper discusses the new requirements and proposes an approach to automate early fault injections targeted towards SET effects.

Keywords

digital circuits; flip-flops; hardware description languages; transients; VHDL descriptions; complex digital circuit; fault injection; functional evaluation; single bit-flip fault model; single event transients; single event upsets; Automata; CMOS technology; Circuit faults; Circuit simulation; Information analysis; Instruments; Logic; Single event transient; Single event upset; Transient analysis; VHDL mutants; dependability analysis; multiple bit flips; single event transients; soft errors;

fLanguage

English

Publisher

ieee

Conference_Titel

Radiation and Its Effects on Components and Systems, 2005. RADECS 2005. 8th European Conference on

Conference_Location

Cap d´Agde

ISSN

0379-6566

Print_ISBN

978-0-7803-9502-2

Electronic_ISBN

0379-6566

Type

conf

DOI

10.1109/RADECS.2005.4365571

Filename

4365571