Solder joints layout design and reliability enhancement of wafer level packaging

During the design and manufacturing processes of electronic packaging, solder joints are fabricated using a variety of methods to provide both mechanical and electrical connections for different applications. They include flip chip, wafer level chip scale packaging (WLCSP), fine pitch ball grid array (BGA), and chip scale packaging (CSP). The solder joint shape prediction methods have been incorporated as a design tool to enhance the reliability of the WLCSP. However, the reliability of solder joints for a large chip size such as 10mm×10mm without underfill remains questionable. In this research, a hybrid method combining an analytical algorithm with the energy-based approach are applied to predict standoff heights and geometry profiles of the solder joints. In additions, a hybrid-pad-shape (HPS) system is proposed to design the solder ball layout, and to enhance the reliability of the solder joints. Next, a nonlinear and parametric finite element analysis is conducted to investigate the reliability issues that result from several design parameters. In addition, an experimental validation is completed to verify the correctness and feasibility of the solder joint shape prediction methods and finite element analysis procedures. The design parameters considered in this study include solder joint layout, solder volume, pad diameter, as well as the ratio and orientation of the elliptical pad. With regards to solder joint layout design, the solder joints located in the corner areas can be considered as structural dummy balls with no electrical signals passing through them. The results reveal that when the WLCSP has large round pads, or properly oriented elliptical solder joint pads at the corner areas underneath the chip, then the maximum equivalent plastic strain of the solder joints is effectively reduced. As a result the solder joint fatigue life under thermal loading is greatly enhanced. Furthermore, the findings of this research can be used as a design guideline for electronic packaging with area array interconnections such as CSP, flip chip packaging, super CSP and fine pitch BGA.